The demand for more reliable analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and related components for use in communication, data acquisition, and battery-operated applications continues to increase. As a result, integrated circuit manufacturers are requiring for such converters and devices to continue to improve their operating performance to meet the design requirements of a myriad of emerging applications.
Capacitor digital-to-analog converters (CDACs) are used frequently in high precision analog-to-digital converter applications. Over the years, many efforts have focused on improvements to the linearity of such CDAC devices. For example, many new techniques have been developed to facilitate the trimming of capacitor values of capacitors C to C/2N−1 within the CDAC to improve linearity. Many applications adjust each capacitor such that the relationship between any two successive capacitors within the array is maintained within a fraction of a least significant bit (LSB) of accuracy, thus maintaining linearity.
Unfortunately, current designs and techniques have generally refrained from addressing gain and offset problems and instead have simply accepted the levels of precision that could be obtained. In some instances, empirical adjustments have been made to the CDAC to improve offset, such as by changing the physical size of pedestal switches to address charge injections and other non-ideal characteristics that can make offset unpredictable. However, such empirical techniques require layout changes and only improve offset to a level that is minimally acceptable, and most importantly do not address gain errors. Accordingly, previous design requirements have demanded less restrictive gain and offset specifications, and focused more on linearity complications.
The range of a CDAC circuit is defined by the smallest value of the input signal that produces a meaningful output signal from the CDAC up to the largest input signal that will produce a meaningful output signal. While linearity is determined by the binary relationship between any two successive capacitors, the range of the CDAC circuit is determined by the amount of capacitance that is sampled versus the total amount of capacitance in the entire CDAC circuit. For example, with reference to FIG. 1, an exemplary CDAC circuit 100 having a capacitor array of 16 bits, e.g., capacitors C to C/215 and sample switches S0-S15, can be configured to enable sampling of sampling voltage VSAMPLE on all 16 capacitors, C to C/215. In addition, to facilitate sampling of CDAC circuit 100, a pedestal switch SP can couple capacitors C to C/215 to a known pedestal voltage VPEDESTAL, with the amount of sampled voltage VSAMPLE equal to a positive sample voltage VPOSITIVE less pedestal voltage VPEDESTAL, i.e., VPOSITIVE−VPEDESTAL. CDAC circuit 100 provides a total capacitance weight of 2C due to the binary weighting, with the range equaling approximately a reference voltage VREF. With reference to FIG. 2, an exemplary CDAC circuit 200 having 16 bits can also be configured to enable sampling of sampling voltage VSAMPLE only on first capacitor C, with the range equaling approximately two times reference voltage VREF, or sampling of sampling voltage VSAMPLE only on second capacitor C/2, with the range equaling approximately four times reference voltage VREF.
In both CDAC circuits 100 and 200, while the range can be configured through a mask change by choosing the particular capacitor to sample on in such a weight as to adjust the range, such CDAC circuits do not allow for correction of gain errors nor offset errors on an individual part basis. Furthermore, in applications in which it is desirable for CDAC circuits to be compatible with older converter circuits, the ability to ideally match process variations, such as the effects caused by input resistor networks that scale the input range, absolutely requires the CDAC circuits to have the ability to correct for the gain and offset. Unfortunately, present CDAC circuits are incapable of such correction techniques.